S/PDIF test generator

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< Analog Electronic ~ S/PDIF test generator

eric

Posted: Mon Oct 09, 2006 11:53 pm Post subject: S/PDIF test generator

Site Admin Joined: 01 Jan 1970 Posts: 311

T. Giesberts
The generator is intended primarily for checking S/PDIF (Sony/
Philips Digital Interface Format) receivers and any associated digital-
to-analogue converters (DAC) and/or output filters. The external
clock – standard TTL level – enables 128 sample frequencies
to be generated. The clock may also be used for generating standard
frequencies with the remaining inverters serving as crystal oscillators
(provided a 74HCU04 is used).
The sender is a Type CS8402A digital audio interface transmitter
from Crystal. In this short article it is not possible to list all
settings that may be obtained with switch S1: the reader is referred
to the data sheet of the IC or to the ‘sampling rate converter’ published
in the October 1996 issue of this magazine. The connections
to the switch are exactly as described in that article.
There is an optical (IC4) as well as a coaxial output (K1, K2).
Toroidal transformer Tr1 provides electrical isolation of the coaxial
sockets and also serves to prevent earth loops. Capacitors C2
and C3 provide the earth connections for the sockets.
The transformer is wound on a TN13/7.5/5-3E25 core with a
transformation ratio of 20:2:2 since TXP and TXN (on IC3) are
differential outputs. The primary voltage is 10 Vpp to give a signal
across the 75 Ω coaxial outputs of 0.5 Vpp. After a reset, both outputs
are low and are not short-circuited by Tr1. A coarse audio signal
is added to prevent, for instance, muting of the outputs.
Jumper JP1 enables either the left-hand or right-hand signal to
contain a rectangular signal at peak value and half the sampling
frequency. This enables, for instance, the channel separation and
the combination of digital and analogue signals to be checked. In
most DACs, filter action commences at half the sampling frequency.
At that instance, there is hardly any attenuation by the
analogue filters, so that the level of the sinusoidal signal more or less
coincides with that of a 0 dB signal. At this frequency, it is also
clearly discernible whether de-emphasis correction is present (S1–4
off: de-emphasis on) and, if so, whether this provides the requisite
attenuation of 10 dB.
The CS8402A is used in mode 0 (low level at inputs M0–M2).
This mode is really intended for interfacing with analogue-to-digital
converters (ADC), but is used here since it enables the FSYNC
of the L/R clock and the bit clock, SCK, to be derived internally
from the MCK clock, and to be arranged as outputs. The data for
half the sampling frequency are obtained by halving the L/R clock
in IC2a. Since the

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