| Author | Message | | | eric | | Posted: Fri Sep 01, 2006 12:45 pm Post subject: PAL timing - part 2 | | | | Site Admin Joined: 01 Jan 1970 Posts: 311 | Design: T. Giesberts
This design is complementary to the design described in the article
‘PAL timing (1)’, which also appears in this issue. It is intended to
derive a line rate signal from a television frame rate
signal, using a PLL. Naturally, this technique can
also be used in situations where the line synchronization
pulses are corrupted.
In the PAL television system, there are 625 lines per
frame. In the PLL circuit, a nominal frequency of
15,625 Hz is thus divided by 625 and then compared
to the 25 Hz input signal. A 74HC4040 (IC2) is
used for the divider. The correct division factor is
obtained with the help of an AND circuit formed
by several diodes, which produces the counter reset
signal (625 decima
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