 | Author | Message | < Programmer ~ DESCRIPTION of IC42S32400L-7BI | | elwen | | Posted: Tue Jul 29, 2008 1:23 am Post subject: DESCRIPTION of IC42S32400L-7BI | | | | Joined: 26 Jun 2008 Posts: 49 | DESCRIPTION of IC42S32400L-7BI:
http://www.chinaicmart.com/series-IC4/IC42S32400L-7BI.html
The ICSI IC42S32400 and IC42S32400L is a high-speed CMOS configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK).
Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ICSI IC42S32400 and IC42S32400L provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions,either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance.These devices are well suited for applications requiring high memory bandwidth. | |
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